1. Field
Aspects of the present invention relate to semiconductor integrated circuits having a test function.
2. Description of Related Art
The structure of semiconductor devices, such as transistors, has been miniaturized and the degree of integration of circuits mounted on one chip has been increasing. Accordingly, a system large-scale integrated circuit (LSI) that realizes functions of a system with one chip has been developed. Generally, a system LSI has a function block (hard macro), such as a memory and a controller, and a user block (user logic) connected to the function block in order to realize functions unique to a user.
An amount of time for testing a system LSI increases in proportion to an increase in the number of logic gates. Such an increase in time leads to an increase in the test cost. Japanese Patent Laid-Open No. 2006-4509 discloses various testing methods for reducing the test cost. To test a user block designed uniquely to a user (to detect a stuck-at fault), a scan path test using daisy-chained flip-flops has been proposed. In addition, to test a function block, such as a memory macro, a method for including a built-in self test (BIST) circuit in a system LSI has been proposed. As described above, an improvement in the efficiency of the test of the user block and the test of the function block is attempted independently.